View AT45DB080-TC_1031180.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features ? single 2.7v - 3.6v supply ? sequential access, parallel i/o architecture ? page program operation C single cycle reprogram (erase and program) C 4096 pages (264 bytes/page) main memory ? two 264-byte data buffers C allows receiving of data while reprogramming of non-volatile memory ? internal program and control timer ? fast page program time C 7 ms typical ? 120 m m m m s typical page to buffer transfer time ? low power dissipation C 4 ma active read current typical C2 m m m m a cmos standby current typical ? 2 mhz max clock frequency ? hardware data protection feature ? synchronous clocking (two modes) ? cmos and ttl compatible inputs and outputs ? commercial and industrial temperature ranges description the at45db080 is a 2.7-volt only, sequential access, parallel interface flash memory suitable for in-system reprogramming. its 8,650,752 bits of memory are organized as 4096 pages of 264-bytes each. in addition to the main memory, the at45db080 also contains two data buffers of 264-bytes each. the buffers allow receiving of data while a page in the main memory is being reprogrammed. unlike conventional flash memo- ries that are accessed randomly with multiple address lines and a parallel interface, 8-megabit 2.7-volt only sequential access parallel i/o dataflash ? at45db080 preliminary rev. 1075bC06/98 (continued) pin configurations pin name function cs chip select clk clock i/o7-i/o0 input/output wp hardware page write protect pin reset chip reset rdy/busy ready/busy soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd nc nc cs clk dc dc nc nc i/o0 i/o1 i/o2 i/o3 gnd vcc nc nc wp reset rdy/busy nc nc nc i/o7 i/o6 i/o5 i/o4 vcc tsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 rdy/busy reset wp nc nc nc vcc gnd nc nc nc nc cs clk dc dc nc nc nc i/o7 i/o6 i/o5 i/o4 vcc gnd i/o3 i/o2 i/o1 i/o0 nc nc nc note: soic pins 6 and 7 and tsop pins 15 and 16 are dont connect.
at45db080 2 the dataflash uses a parallel interface to sequentially access its data. the simple sequential access facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. the device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. typical applications for the dataflash are digital voice storage, image storage, and data storage. the device operates at clock frequencies up to 2 mhz with a typical active read current consumption of 4 ma. to allow for simple in-system reprogrammability, the at45db080 does not require high input voltages for pro- gramming. the device operates from a single power sup- ply, 2.7v to 3.6v, for both the program and read operations. the at45db080 is enabled through the chip select pin (cs ) and accessed via an interface consisting of the parallel input/output (i/o7-i/o0) pins and the clock (clk) pin. all programming cycles are self-timed, and no separate erase cycle is required before programming. block diagram device operation the device operation is controlled by instructions from the host processor. the list of instructions and their associated opcodes are contained in table 1 and table 2. a valid instruction starts with the falling edge of cs followed by the appropriate 1-byte opcode and the desired buffer or main memory address location. while the cs pin is low, toggling the clk pin controls the loading of the opcode and the desired buffer or main memory address location through the input pins (i/o7-i/o0). read by specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers. main memory page read: a main memory read allows the user to read data directly from any one of the 4096 pages in the main memory, bypassing both of the data buff- ers and leaving the contents of the buffers unchanged. to start a page read, the 1-byte opcode, 52h, is followed by 3 address bytes (which comprise the 24 page and byte address bits) and 60 dont care bytes. in the at45db080, the first three address bits are reserved for larger density devices (see notes on page 8), the next 12 address bits (pa11-pa0) specify the page address, and the next nine address bits (ba8-ba0) specify the starting byte address within the page. the 60 dont care bytes which follow the 3 address bytes are sent to initialize the read operation. fol- lowing the 60 dont care bytes, additional pulses on clk result in data being output on the output pins (i/o7-i/o0). the cs pin must remain low during the loading of the opcode, the address bytes, the dont care bytes, and the reading of data. when the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginning of the same page. a low to high transition on the cs pin will terminate the read oper- ation and tri-state the output pins. buffer read: data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. an opcode of 54h is used to read data from buffer 1, and an opcode of 56h is used to read data from flash memory array page (264 bytes) buffer 2 (264 bytes) buffer 1 (264 bytes) i/o interface clk cs reset v cc gnd rdy/busy wp i/o7-i/o0
at45db080 3 buffer 2. to perform a buffer read, the 1-byte opcode must be followed by the three address bytes comprised of 15 dont care bits and nine address bits. following the three address bytes, an additional dont care byte must be clocked in to initialize the read operation. since the buffer size is 264-bytes, nine address bits (bfa8-bfa0) are required to specify the first byte of data to be read from the buffer. the cs pin must remain low during the loading of the opcode, the address bytes, the dont care bytes, and the reading of data. when the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. a low to high transition on the cs pin will termi- nate the read operation and tri-state the output pins. main memory page to buffer transfer: a page of data can be transferred from the main memory to either buffer 1 or buffer 2. a 1-byte opcode, 53h for buffer 1 and 55h for buffer 2, is followed by the three address bytes comprised of the three reserved bits, 12 address bits (pa11-pa0) which specify the page in main memory that is to be transferred, and nine dont care bits. the cs pin must be low while toggling the clk pin to load the opcode and the address bytes from the input pins. the transfer of the page of data from the main memory to the buffer will begin when the cs pin transitions from a low to a high state. dur- ing the transfer of a page of data (t xfr ), the status register can be read to determine whether the transfer has been completed or not. main memory page to buffer compare: a page of data in main memory can be compared to the data in buffer 1 or buffer 2. a 1-byte opcode, 60h for buffer 1 and 61h for buffer 2, is followed by three address bytes consisting of three reserved bits, 12 address bits (pa11-pa0) which specify the page in the main memory that is to be com- pared to the buffer, and nine don't care bits. the loading of the opcode and the address bits is the same as described previously. the cs pin must be low while toggling the clk pin to load the opcode and the address bytes from the input pins. on the low to high transition of the cs pin, the 264 bytes in the selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2. during this time (t xfr ), the status register will indicate that the part is busy. on completion of the compare operation, bit 6 of the status register is updated with the result of the compare. program buffer write: data can be clocked in from the input pins into either buffer 1 or buffer 2. to load data into either buffer, a 1-byte opcode, 84h for buffer 1 or 87h for buffer 2, is followed by the three address bytes comprised of 15 don't care bits and nine address bits (bfa8-bfa0). the nine address bits specify the first byte in the buffer to be written. the data is entered following the address bits. if the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. data will con- tinue to be loaded into the buffer until a low to high transi- tion is detected on the cs pin. buffer to main memory page program with built-in erase: data written into either buffer 1 or buffer 2 can be programmed into the main memory. a 1-byte opcode, 83h for buffer 1 or 86h for buffer 2, is followed by the three address bytes consisting of three reserved bits, 12 address bits (pa11-pa0) that specify the page in the main memory to be written, and nine additional don't care bits. when a low-to-high transition occurs on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the programming of the page are internally self timed and should take place in a maximum time of t ep . during this time, the status register will indicate that the part is busy. buffer to main memory page program with- out built-in erase: a previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. a 1-byte opcode, 88h for buffer 1 or 89h for buffer 2, is followed by three address bytes con- sisting of three reserved bits, 12 address bits (pa11-pa0) that specify the page in the main memory to be written, and nine additional dont care bits. when a low to high transition occurs on the cs pin, the part will program the data stored in the buffer into the specified page in the main memory. it is necessary that the page in main memory that is being programmed has been previously programmed to all 1s (erased state). the programming of the page is internally self timed and should take place in a maximum time of t p . during this time, the status register will indicate that the part is busy. main memory page program: this operation is a combination of the buffer write and buffer to main memory page program with built-in erase operations. data is first clocked into buffer 1 or buffer 2 from the input pins and then programmed into a specified page in the main mem- ory. a 1-byte opcode, 82h for buffer 1 or 85h for buffer 2, is followed by three address bytes comprised of three reserved bits and 21 address bits. the 12 most significant address bits (pa11-pa0) select the page in the main mem- ory where data is to be written, and the next nine address bits (bfa8-bfa0) select the first byte in the buffer to be written. after all address bytes are clocked in, the part will take data from the input pins and store it in one of the data buffers. if the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. when there is a low to high transition on the cs pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. both the erase and the program- ming of the page are internally self timed and should take place in a maximum of time t ep . during this time, the status register will indicate that the part is busy.
at45db080 4 auto page rewrite: this mode is only needed if multi- ple bytes within a page or multiple pages of data are modi- fied in a random fashion. this mode is a combination of two operations: main memory page to buffer transfer and buffer to main memory page program with built-in erase. a page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. a 1-byte opcode, 58h for buffer 1 or 59h for buffer 2, is followed by the three address bytes comprised of three reserved bits, 12 address bits (pa11-pa0) that specify the page in main memory to be rewritten, and nine additional don't care bits. when a low to high transition occurs on the cs pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. the operation is internally self-timed and should take place in a maximum time of t ep . during this time, the status regis- ter will indicate that the part is busy. if the main memory is programmed or reprogrammed sequentially page by page, then the programming algo- rithm shown in figure 1 is recommended. otherwise, if multiple bytes in a page or several pages are programmed randomly in the main memory, then the programming algo- rithm shown in figure 2 is recommended. status register: the status register can be used to determine the devices ready/busy status, the result of a main memory page to buffer compare operation, or the device density. to read the status register, an opcode of 57h must be loaded into the device. after the opcode is clocked in, the 1-byte status register will be clocked out on the output pins during the next clock cycle. the five most- significant bits of the status register will contain device information, while the remaining three least-significant bits are reserved for future use and will have undefined values. after the one byte of the status register has been clocked out, the sequence will repeat itself (as long as cs remains low and clk is being toggled). the data in the status regis- ter is constantly updated, so each repeating sequence will output new data. ready/busy status is indicated using bit 7 of the status reg- ister. if bit 7 is a 1, then the device is not busy and is ready to accept the next command. if bit 7 is a 0, then the device is in a busy state. the user can continuously poll bit 7 of the status register on i/o7 by stopping clk once bit 7 has been output on i/o7. the status of bit 7 will continue to be output on the i/o7 pin, and once the device is no longer busy, the state of i/o7 will change from 0 to 1. there are six operations which can cause the device to be in a busy state: main memory page to buffer transfer, main memory page to buffer compare, buffer to main memory page pro- gram with built-in erase, buffer to main memory page pro- gram without built-in erase, main memory page program, and auto page rewrite. the result of the most recent main memory page to buffer compare operation is indicated using bit 6 of the status register. if bit 6 is a 0, then the data in the main memory page matches the data in the buffer. if bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. the device density is indicated using bits 5, 4, and 3 of the status register. for the at45db080, the three bits are 1, 0, and 0. the decimal value of these three binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of serial dataflash devices, allowing a total of eight different density configurations. read/program mode summary the modes listed above can be separated into two groups modes which make use of the flash memory array (group a) and modes which do not make use of the flash memory array (group b). group a modes consist of: 1. main memory page read 2. main memory page to buffer 1 (or 2) transfer 3. main memory page to buffer 1 (or 2) compare 4. buffer 1 (or 2) to main memory page program with built-in erase 5. buffer 1 (or 2) to main memory page program with- out built-in erase 6. main memory page program 7. auto page rewrite group b modes consist of: 1. buffer 1 (or 2) read 2. buffer 1 (or 2) write 3. status read if a group a mode is in progress (not fully completed) then another mode in group a should not be started. however, during this time in which a group a mode is in progress, modes in group b can be started. this gives the serial dataflash the ability to virtually accommodate a continuous data stream. while data is being programmed into main memory from buffer 1, data status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdy/busy comp100xxx
at45db080 5 can be loaded into buffer 2 (or vice versa). see application note an-4 (using atmels serial dataflash) for more details. hardware page write protect: if the wp pin is held low, the first 256 pages of the main memory cannot be reprogrammed. the only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. the wp pin is internally pulled high; therefore, in low pin count applica- tions, connection of the wp pin is not necessary if this pin and feature will not be utilized. however, it is recom- mended that the wp pin be driven high externally when- ever possible. reset : a low state on the reset pin (reset ) will terminate the operation in progress and reset the internal state machine to an idle state. the device will remain in the reset condition as long as a low level is present on the reset pin. normal operation can resume once the reset pin is brought back to a high level. the device incorporates an internal power-on reset circuit, so there are no restrictions on the reset pin during power-on sequences. the reset pin is also internally pulled high; therefore, in low pin count applications, con- nection of the reset pin is not necessary if this pin and feature will not be utilized. however, it is recommended that the reset pin be driven high externally whenever possible. ready/busy : this open drain output pin will be driven low when the device is busy in an internally self-timed oper- ation. this pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during program- ming operations, compare operations, and during page-to- buffer transfers. the busy status indicates that the flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. power on/reset state when power is first applied to the device, or when recover- ing from a reset condition, the device will default to the inactive clock polarity high mode. in addition, the output pins (i/o 7 - i/o 0 ) will be in a high impedance state, and a high to low transition on the cs pin will be required to start a valid instruction. the clock polarity mode will be auto- matically selected on every falling edge of cs by sampling the inactive clock state. note: 1. after power is applied and v cc is at the minimum specified data sheet value, the system should wait 20 ms before an oper- ational mode is started. absolute maximum ratings* temperature under bias.......................-55 c to +125 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature............................-65 c to +150 c all input voltages (including nc pins) with respect to ground......................... -0.6v to +6.25v all output voltages with respect to ground................... -0.6v to v cc + 0.6v dc and ac operating range at45db081 operating temperature (case) com. 0 c to 70 c ind. -40 c to 85 c v cc power supply (1) 2.7v to 3.6v
at45db080 6 dc characteristics symbol parameter condition min typ max units i sb standby current cs , reset , wp = v ih , all inputs at cmos levels 210 m a i cc1 active current, read operation f = 2 mhz; i out = 0 ma; v cc = 3.6v 410ma i cc2 active current, program/erase operation 15 35 ma i li input load current v in = 0v to v cc 1 m a i lo output leakage current v i/o = 0v to v cc 1 m a v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 1.6 ma; v cc = 2.7v 0.4 v v oh output high voltage i oh = -100 m av cc - 0.2v v ac characteristics symbol parameter min typ max units f sck sck frequency 2mhz t wh sck high time 200 ns t wl sck low time 200 ns t cs minimum cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns t csb cs high to rdy/busy low 200 ns t su data in setup time 20 ns t h data in hold time 50 ns t ho output hold time 0 ns t dis output disable time 150 ns t v output valid 180 ns t xfr page to buffer transfer/compare time 120 250 m s t ep page erase and programming time 10 20 ms t p page programming time 7 14 ms t rst reset pulse width 10 m s t rec reset recovery time 1 m s input test waveforms and measurement levels t r , t f < 20 ns (10% to 90%) ac driving levels ac measurement level 0.45v 2.0 0.8 2.4v output test load device under test 30 pf
at45db080 7 ac waveforms two different timing diagrams are shown below. waveform 1 shows the clk signal being low when cs makes a high- to-low transition, and waveform 2 shows the clk signal being high when cs makes a high-to-low transition. both waveforms show valid timing diagrams. the setup and hold times for the si signal are referenced to the low-to-high transition on the clk signal. waveform 1 C inactive clock polarity low waveform 2 C inactive clock polarity high cs clk i/o7-i/o0 (input) i/o7-i/o0 (output) tcss valid in th tsu twh twl tcsh tcs tv high impedance valid out tho tdis high impedance cs clk i/o7-i/o0 (input) i/o7-i/o0 (output) tcss valid in th tsu twl twh tcsh tcs tv high z valid out tho tdis high impedance
at45db080 8 reset timing (inactive clock polarity low shown) command sequence for read/write operations (except status register read) notes: 1. r designates bits reserved for larger densities. 2. it is recommended that r be a logical 0 for densities of 8m bit or smaller. 3. for densities larger than 8m bit, the r bits become the most significant page address bit for the appropriate density. cs sck reset so high impedance high impedance si trst trec tcss i/o7-i/o0 (input) cmd addr addr addr msb reserved for larger densities page address (pa11-pa0) byte/buffer address (ba8-ba0/bfa8-bfa0) lsb r r r x x x x x x x x x x x x x x x x x x x x x
at45db080 9 write operations the following block diagram and waveforms illustrate the various write sequences available. main memory page program through buffers buffer write buffer to main memory page program (data from buffer programmed into flash page) flash memory array page (264 bytes) buffer 2 (264 bytes) buffer 1 (264 bytes) i/o interface i/o7-i/o0 (input) buffer 1 to main memory page program main memory page program through buffer 2 buffer 2 to main memory page program main memory page program through buffer 1 buffer 1 write buffer 2 write i/o7-i/o0 (input) cmd n n+1 last byte completes writing into selected buffer starts self-timed erase/program operation cs r r r, pa11-7 pa6-0, bfa8 bfa7-0 addr addr addr i/o7-i/o0 (input) cmd x xx, bfa8 bfa7-0 n n+1 last byte completes writing into selected buffer cs addr addr addr i/o7-i/o0 (input) cmd pa6-0, x cs starts self-timed erase/program operation r r r, pa11-7 x addr addr addr each transition represents 8 bits and 1 clock cycle n = 1st byte written n+1 = 2nd byte written
at45db080 10 read operations the following block diagram and waveforms illustrate the various read sequences available. main memory page read main memory page to buffer transfer (data from flash page read into buffer) buffer read flash memory array page (264 bytes) buffer 2 (264 bytes) buffer 1 (264 bytes) i/o interface main memory page to buffer 1 main memory page to buffer 2 main memory page read buffer 1 read buffer 2 read i/o7-i/o0 (output) i/o7-i/o0 (input) cmd pa6-0, ba8 ba7-0 x x x x cs n n+1 i/o7-i/o0 (output) r r r, pa11-7 addr addr addr i/o7-i/o0 (input) cmd pa6-0, x x starts reading page data into buffer cs i/o7-i/o0 (output) r r r, pa11-7 addr addr addr i/o7-i/o0 (input) cmd x xx, bfa8 bfa7-0 cs n n+1 i/o7-i/o0 (output) x addr addr addr each transition represents 8 bits and 1 clock cycle n = 1st byte written n+1 = 2nd byte written
at45db080 11 detailed read timing C inactive clock polarity low main memory page read buffer read status register read i/o7-i/o0 (input) cmd addr addr addr x xxx cs i/o7-i/o0 (output) clk 1 2345 60 61 62 63 64 65 66 67 xx high-impedance data data data data out tsu tv i/o7-i/o0 (input) cmd addr addr addr x cs i/o7-i/o0 (output) clk 1 2345 678 high-impedance data data data data out tsu tv i/o7-i/o0 (input) cmd cs i/o7-i/o0 (output) clk 1 234 high-impedance high-impedance data data data status register output tsu tv
at45db080 12 detailed read timing C inactive clock polarity high main memory page read buffer read status register read i/o7-i/o0 (input) cmd addr addr addr x xxx cs i/o7-i/o0 (output) clk 1 2345 61 62 63 64 65 66 67 xx high-impedance data data data data out tsu tv data 68 i/o7-i/o0 (input) cmd addr addr addr x cs i/o7-i/o0 (output) clk 1 2345 678 high-impedance data data data data out tsu tv data 9 i/o7-i/o0 (input) cmd cs i/o7-i/o0 (output) clk 1 234 high impedance high impedance data data data status register output tsu tv x (dont care) r (reserved bits)
at45db080 13 table 1. main memory page read buffer 1 read buffer 2 read main memory page to buffer 1 transfer main memory page to buffer 2 transfer main memory page to buffer 1 compare main memory page to buffer 2 compare buffer 1 write buffer 2 write opcode clk i/o 52h 54h 56h 53h 55h 60h 61h 84h 87h 1 70 00 0 0 0 0 11 61 11 1 1 1 1 00 50 00 0 0 1 1 00 41 11 1 1 0 0 00 30 00 0 0 0 0 00 20 11 0 1 0 0 11 11 01 1 0 0 0 01 00 00 1 1 0 1 01 2 7rxxrrrrxx 6rxxrrrrxx 5rxxrrrrxx 4 pa11 x x pa11 pa11 pa11 pa11 x x 3 pa10 x x pa10 pa10 pa10 pa10 x x 2 pa9 x x pa9 pa9 pa9 pa9 x x 1 pa8 x x pa8 pa8 pa8 pa8 x x 0 pa7 x x pa7 pa7 pa7 pa7 x x 3 7 pa6 x x pa6 pa6 pa6 pa6 x x 6 pa5 x x pa5 pa5 pa5 pa5 x x 5 pa4 x x pa4 pa4 pa4 pa4 x x 4 pa3 x x pa3 pa3 pa3 pa3 x x 3 pa2 x x pa2 pa2 pa2 pa2 x x 2 pa1 x x pa1 pa1 pa1 pa1 x x 1 pa0 x x pa0 pa0 pa0 pa0 x x 0 ba8 bfa8 bfa8 x x x x bfa8 bfa8 4 7 ba7 bfa7 bfa7 x x x x bfa7 bfa7 6 ba6 bfa6 bfa6 x x x x bfa6 bfa6 5 ba5 bfa5 bfa5 x x x x bfa5 bfa5 4 ba4 bfa4 bfa4 x x x x bfa4 bfa4 3 ba3 bfa3 bfa3 x x x x bfa3 bfa3 2 ba2 bfa2 bfa2 x x x x bfa2 bfa2 1 ba1 bfa1 bfa1 x x x x bfa1 bfa1 0 ba0 bfa0 bfa0 x x x x bfa0 bfa0 5 7x xx 6x xx 5x xx 4x xx 3x xx 2x xx 1x xx 0x xx ? ? ? ? ? ? 64 7x 6x 5x 4x 3x 2x 1x 0x x (dont care) r (reserved bits)
at45db080 14 table 2. buffer 1 to main memory page program with built- in erase buffer 2 to main memory page program with built- in erase buffer 1 to main memory page program without built-in erase buffer 2 to main memory page program without built-in erase main memory page program through buffer 1 main memory page program through buffer 2 auto page rewrite through buffer 1 auto page rewrite through buffer 2 status register opcode clk i/o 83h 86h 88h 89h 82h 85h 58h 59h 57h 1 7111111000 6000000111 5000000000 4000000111 3001100110 2010001001 1110010001 0100101011 2 7rrrrrrrr 6rrrrrrrr 5rrrrrrrr 4pa11pa11pa11pa11pa11pa11pa11pa11 3pa10pa10pa10pa10pa10pa10pa10pa10 2 pa9 pa9 pa9 pa9 pa9 pa9 pa9 pa9 1 pa8 pa8 pa8 pa8 pa8 pa8 pa8 pa8 0 pa7 pa7 pa7 pa7 pa7 pa7 pa7 pa7 3 7 pa6 pa6 pa6 pa6 pa6 pa6 pa6 pa6 6 pa5 pa5 pa5 pa5 pa5 pa5 pa5 pa5 5 pa4 pa4 pa4 pa4 pa4 pa4 pa4 pa4 4 pa3 pa3 pa3 pa3 pa3 pa3 pa3 pa3 3 pa2 pa2 pa2 pa2 pa2 pa2 pa2 pa2 2 pa1 pa1 pa1 pa1 pa1 pa1 pa1 pa1 1 pa0 pa0 pa0 pa0 pa0 pa0 pa0 pa0 0xxxxba8ba8xx 4 7xxxxba7ba7xx 6xxxxba6ba6xx 5xxxxba5ba5xx 4xxxxba4ba4xx 3xxxxba3ba3xx 2xxxxba2ba2xx 1xxxxba1ba1xx 0xxxxba0ba0xx
at45db080 15 figure 1. algorithm for programming or reprogramming of the entire array sequentially notes: 1. this type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by- page. 2. a page can be written using either a main memory page program operation or a buffer write operation followed by a buffer to main memory page program operation. 3. the algorithm above shows the programming of a single page. the algorithm will be repeated sequentially for each page within the entire array. start main memory page program (82h, 85h) end provide address and data buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
at45db080 16 figure 2. algorithm for randomly modifying data note: 1. to preserve data integrity, each page of the dataflash memory array must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations. 2. a page address pointer must be maintained to indicate which page is to be rewritten. the auto page rewrite command must use the address specified by the page address pointer. 3. other algorithms can be used to rewrite portions of the flash array. low power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all pages of the flash array. see application note an-4 (using atmels serial dataflash) for more details. start main memory page to buffer transfer (53h, 55h) increment page address pointer (2) auto page rewrite (2) (58h, 59h) end provide address of page to modify if planning to modify multiple bytes currently stored within a page of the flash array main memory page program (82h, 85h) buffer write (84h, 87h) buffer to main memory page program (83h, 86h)
at45db080 17 ordering information f sck (mhz) i cc (ma) ordering code package operation range active standby 2 10 0.01 at45db080-rc AT45DB080-TC 28r 32t commercial (0 c to 70 c) 2 10 0.01 at45db080-ri at45db080-ti 28r 32t industrial (-40 c to 85 c) package type 28r 28-lead, 0.330" wide, plastic gull-wing small outline package (soic) 32t 32-lead, plastic thin small outline package (tsop)
at45db080 18 packaging information *controlling dimension: millimeters index mark 18.5(.728) 18.3(.720) 20.2(.795) 19.8(.780) 0.25(.010) 0.15(.006) 0.50(.020) bsc 7.50(.295) ref 8.20(.323) 7.80(.307) 1.20(.047) max 0.15(.006) 0.05(.002) 0 5 ref 0.70(.028) 0.50(.020) 0.20(.008) 0.10(.004) 28r, 28-lead, 0.330" wide, plastic gull wing small outline package (soic) dimensions in inches and (millimeters) 32t, 32-lead, plastic thin small outline package (tsop) dimensions in millimeters and (inches)*

▲Up To Search▲

Price & Availability of AT45DB080-TC

	To Download AT45DB080-TC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .